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01_a3b_nor_aus_nand.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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02_a3c_not_aus_nand.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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03_a3d_and_aus_nand.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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04_a3e_or_aus_nand.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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05_a3f_xor_aus_nand.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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06_a4a_d_flipflop_1.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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07_a4a_rs_flipflop.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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08_a4b_d_flipflop_2.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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09_a5_4bit-xor.mod
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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10_a5a_4bit-xor.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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11_a5b_xor.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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12_a6a_halbaddierer.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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12_a6b_halbaddierer.mod
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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13_a7a_volladdierer.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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14_a7b_8bit_addierer.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
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15_a9_4bit_addierer.lsim
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Initial commit
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2025-01-05 09:08:13 +01:00 |
